System Refresh in Cache Memory

ABSTRACT

System refresh in a cache memory includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory, activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory, receiving a refresh grant in response to activating the refresh request, and transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.

BACKGROUND

This invention generally relates to cache memory, and in particular, tosystem refresh in cache memory.

Embedded dynamic random access memory (EDRAM) requires periodic refreshoperations to retain contents of memory cells. The period of therequired refresh operations varies depending upon system temperature andvoltage level. In a relatively large cache system, there may beconsiderable distance and latency separating a cache controller from thecache itself. The distances and larger number of EDRAM macros associatedwith large caches may provide added difficulties with regards to noise,voltage requirements, and latency. For example, if a relatively largenumber of EDRAM macros were to be refreshed simultaneously, a spike innoise may be formed which could affect performance of the cache memory.Additionally, supply voltage to other portions of the cache memory maybe depleted in large refresh operations which may further affectperformance of the cache memory. Moreover, tracking and scheduling ofsystem refresh operations may be hindered by the increased latencybetween a cache control and those cache memory banks furthest away.

SUMMARY

An example embodiment of the present invention includes a computerprogram product for system refresh in a cache memory, comprising atangible storage medium readable by a processing circuit and storinginstructions for execution by the processing circuit for performing amethod. The method includes generating a refresh time period (RTIM)pulse at a centralized refresh controller of the cache memory,activating a refresh request at the centralized refresh controller inresponse to generating the RTIM pulse, the refresh request associatedwith a single cache memory bank of the cache memory, receiving a refreshgrant in response to activating the refresh request, and transmittingthe refresh grant to a bank controller, the bank controller associated,and localized, at the single cache memory bank of the cache memory.

An example embodiment of the present invention includes a system forrefresh in a cache memory. The system includes at least one cache memorybank, a bank controller local to, and in communication with, the atleast one cache memory bank, and a centralized refresh controller incommunication with the bank controller. The centralized refreshcontroller configured to perform a method including generating a refreshtime period (RTIM) pulse at the centralized refresh controller of thecache memory, activating a refresh request at the centralized refreshcontroller in response to generating the RTIM pulse, the refresh requestassociated with the at least one cache memory bank, receiving a refreshgrant in response to activating the refresh request, and transmittingthe refresh grant to the bank controller.

An example embodiment of the present invention includes a computerimplemented method of system refresh in a cache memory. The methodincludes generating a refresh time period (RTIM) pulse at a centralizedrefresh controller of the cache memory, activating a refresh request atthe centralized refresh controller in response to generating the RTIMpulse, the refresh request associated with a single cache memory bank ofthe cache memory, receiving a refresh grant in response to activatingthe refresh request, and transmitting the refresh grant to a bankcontroller, the bank controller associated, and localized, at the singlecache memory bank of the cache memory

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with advantagesand features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alikein the several FIGURES:

FIG. 1 depicts a state of the art cache topology;

FIG. 2 depicts a logical layout of a single cache chip;

FIG. 3 depicts a logical view of a single cache bank;

FIG. 4 depicts a cache controller with system refresh;

FIG. 5 depicts a central refresh controller;

FIG. 6 depicts a method of cache refresh;

FIG. 7 depicts a method of cache refresh; and

FIG. 8 depicts a computer program product.

DETAILED DESCRIPTION

An example embodiment of the present invention provides cache refreshoptimized for large cache memories. According to example embodiments, acache refresh system may include a centralized cache refresh controllerdisposed to track and satisfy the refresh requirements of independentcache banks. The cache refresh system employs a bank availability modelwhich is configured to monitor command and transfer phases of operationswithin cache memory banks to determine bank availability, and furtherconfigured to grant refresh requests from the centralized cache refreshcontroller based on the monitoring and availability. The refresh requestgrants are communicated to bank controllers localized at each cachememory bank.

Technical effects and benefits of example embodiments of the presentinvention include the centralized control of system refresh operationsfor an entire cache memory chip including a bank availability model usedin determining if a refresh command is appropriate, resulting in smallerprocessing pipeline gaps for refresh commands with less pipeline idletime, and increased productivity.

FIG. 1 illustrates a state of the art cache topology 100. FIG. 1illustrates a plurality of central processors (CP) 105 (e.g., centralprocessing units) operatively connected via busses to one or more L4caches 110. Although not shown in FIG. 1, each of the central processors105 includes one or more cores which may perform reading and executingof instructions. On each central processor 105, the multiple cores maybe operatively connected via busses to the L1, L2, and L3 caches 125,120, and 115. The L1 caches 125 are physically closest to the cores,with the L2 caches 120 and the L3 caches 115 successively further fromthe cores. It is understood that the designation of caches may bereversed. Although the L3 and L4 caches 115 and 110 may compriseembedded dynamic random access memory (DRAM) which is referred to hereinas EDRAM, it should be understood that any other type of suitablememory, such as DRAM, may be utilized. The plurality of centralprocessors 105 operatively connected to the L4 caches 110 (e.g., two L4caches) form a node 150. In a computing system, a plurality of nodes 150may be operatively connected to one another for communications such asmaking and responding to requests, or any suitable operation.

Each individual central processor 105 may be fabricated on a separatechip, which may include the L1, L2, and L3 caches 125, 120, and 115. TheL4 cache 110 may be fabricated on a separate chip, or a combination ofseparate chips. According to example embodiments of the presentinvention, the L4 cache 110 is formed on two (2) separate chips.Fabrication of the chips (including integrated circuits, wires, metallayers, semiconductor and/or other material components) may befacilitated through lithography and/or other suitable techniques. Thefabrication process may include various deposition techniques includingphysical vapor deposition (PVD), chemical vapor deposition (CVD),electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomiclayer deposition (ALD) and/or any suitable technique.

Turning to FIG. 2, a logical layout of a single cache chip isillustrated. For example, the cache may be a L4 cache. It should beunderstood that according to at least one example embodiment, an entirecache is divided amongst two chips, and therefore, a complete examplecache would include two chips 200. A single chip 200 may include sixteencache banks, divided into EVEN and ODD sections, labeled 0-15 EVEN/ODD(204). The cache banks 204 may each include a local bank controller 205.The local bank controller 205 may direct refresh operations for eachEDRAM macro within an associated cache memory bank.

The chip 200 may also include data flow portions 201 and 202. The dataflow portions 201 and 202 may include buffers and multiplexors (notillustrated for the sake of clarity) to facilitate data flow across thechip 200.

The chip 200 may further include a cache control and directory 203. Thecache control and directory 203 provides control of cache reads/writes.The cache control and directory 203 includes a central refreshcontroller 231. The cache control and directory may also include a bankavailability model (illustrated in FIG. 4) facilitating the creation ofa model representing a cache bank's availability.

The central refresh controller 231 may be in communication with theplurality of bank controllers 205, the bank availability model, and theplurality of array built-in self test (ABIST) controllers 206.Therefore, the central refresh controller 231 may determine and trackrefresh requirements for each of the plurality of bank controllers 205,thereby facilitating system refresh commands based on a model of eachbank's availability without the drawbacks of latency involved in directrequests from each cache memory bank.

FIG. 3 depicts a logical view of a single L4 cache bank. The cache bank300 includes a plurality of EDRAM macros 301-303. The plurality of EDRAMmacros 301-303 are divided into twenty-four (24) compartments arrangedin three rows, labeled ROW 1, ROW 2, and ROW 3. ROW 1 includes theplurality of EDRAM macros 301, and provides eight compartments 0 through7. ROW 2 includes the plurality of EDRAM macros 302, and provides eightcompartments 8 through 15. ROW 3 includes the plurality of EDRAM macros303, and provides eight compartments 16 through 23. Each EDRAM macro andconsequently each ROW contains 1024 lines, addressable via 10 lineaddress bits (not shown for clarity).

The cache bank 300 receives store data over a plurality of communicationbuses 310. The store data is stored in associated EDRAMS depending uponan associated compartment and line addresses. The cache bank 300transfers fetched data over a plurality of communication buses 311. Eachcommunication bus of the plurality of communication buses 310-311 may bea 16 byte wide communication bus comprised of individual 9-bit widecommunication buses.

The cache bank additionally includes a local bank controller 304. Thebank controller is in communication with the plurality of EDRAM macros301-303, and may issues refresh commands for the plurality of EDRAMmacros 301-303 as requests are granted by the central refresh controller231. The bank controller 304 receives commands for functional accessesfrom a final pipe priority control macro over communication bus 305. Thebank controller 304 receives ABIST commands from ABIST controllers overcommunication bus 306. The bank controller 304 receives refresh commandsover communication bus 307.

Hereinafter, system refresh control is described more fully withreference to FIGS. 4-5.

FIG. 4 depicts a cache controller with system refresh. The cachecontroller 400 may include a plurality of transaction controllers 401.The plurality of transaction controllers 401 compete for access to thecache transaction pipeline. Different types of transactions havedifferent resource requirements for successful completion of a pipemass.

The cache controller 400 further includes pipe request filtering unit402 in communication with the transaction controllers 401. The filteringunit 402 filters requests based on the availability of the resources therequests require. The filtering unit 402 receives requests from thetransaction controllers 401 and receives resource availability vectorsfrom both an EDRAM availability model 404 and other resourceavailability vectors 413.

The cache controller 400 further includes pipe request arbitration unit403. The arbitration unit 403 is a multi-level arbiter which isconfigured to choose a single filtered request for entry into thetransaction pipeline for every cycle there is an active filteredrequest. Cache access commands from the arbitrations unit 403 are sentto bank controllers over communications bus 412.

The cache controller 400 further includes the EDRAM bank availabilitymodel 404 in communication with the filtering unit 402 and thearbitration unit 403. The cache controller 400 further includes acentral refresh controller 405 in communication with the EDRAM bankavailability model 404.

The bank availability model 404 receives refresh request vectors fromthe central refresh controller 405. The EDRAM availability model 404transmits refresh grant vectors to the central refresh controller 405 inresponse to the request vectors. For example, the EDRAM bankavailability model 403 provides bank availability vectors for both storeand fetch operations to the filtering unit 402. Filtered requests areprovided from the filtering unit 402 to the arbitration unit 403. Thearbitration unit 403 provides information related to a chosen singlefiltered request to the EDRAM bank availability model 404, such that theEDRAM bank availability model may determine which refresh requestscontained in received refresh requests vectors may be granted.Thereafter, the EDRAM bank availability model returns the grantedrequests as a vector to the central refresh controller 405. The centralrefresh controller transmits associated refresh commands to bankcontrollers over communication bus 410.

According to example embodiments, the bank availability model 404 tracksthe cache resources needed for various operations at each cache bank.For example, a fetch operation to a bank may require multiple cycles toexecute the fetch command before fetch data is available, followed bymultiple cycles of data delivery on the fetch bus dedicated to thatbank. Further, a store operation requires multiple cycles of datadelivery on the store bus dedicated to that bank, followed by multiplecycles to execute the store command once all the data has beendelivered. Further, a refresh operation requires multiple cycles tocomplete, but includes no data transfer cycles. The EDRAM macros (andconsequently the cache bank they comprise) are capable of simultaneouslyaccumulating store data for one operation while delivering fetch datafor a different operation. Likewise, the execution of the command phaseof an operation (e.g., fetch, store, or refresh) may occur during thedata transfer phase of a different operation. However, the command phaseof any operation may not overlap the command phase of another operation.The bank availability model 404 uses shift registers and counters tomodel the resource usage at a bank during the data delivery and commandexecution phases of all operations. Based on the operations in progress,the bank model broadcasts the bank availability vectors for every bankin the cache to the filtering unit 413. These availability vectors areused to filter requests for bank access by a plurality of cachecontrollers, each of which may be dynamically dedicated to a singlerequest on behalf of a microprocessor of a computer system.

Hereinafter, a more detailed description of a central refresh controlleris provided with reference to FIG. 5.

FIG. 5 depicts a central refresh controller. The central refreshcontroller 500 may include a normal refresh register 501 and a fastrefresh register 502. The normal refresh register 501 may provide arefresh frequency value for typical system operating conditions. Thefast refresh register 502 may provide an increased refresh frequencyvalue. For example, an increased refresh frequency may be necessary inthe event of cooling system malfunctions, environmental changes, orother events which would otherwise reduce the amount of time values arestable within an EDRAM macro.

The central refresh controller 500 further includes RTIM multiplexor 503in communication with both the normal refresh register 501 and the fastrefresh register 502. The RTIM multiplexor 503 facilitates selectionbetween normal and fast refresh frequency values.

The central refresh controller further includes refresh period unit 504in communication with the RTIM multiplexor 503. The unit 504 provides arefresh period based on the selected frequency. It is noted that theelements 501-504 may be single elements within the central refreshcontroller 500, while the remaining elements illustrated may beimplemented once for each cache memory bank. For example, the centralrefresh controller may be sliced into portions representing each cachememory bank. Each of the sliced portions may include implementations ofelements 505-511 described below, while elements 501-504 are common toall sliced portions. The description provided below thus isrepresentative of a single cache memory bank, and the simplifiedillustration representing one sliced portion is intended to beillustrative only. It should be understood that several implementationsof the elements 505-511 are necessary for cache refresh control of morethan one cache bank.

Returning to FIG. 5, the refresh period from unit 504 is compared to arefresh count through comparator 505, the output of which is active whenboth inputs are equal, resulting in a single cycle pulse that isforwarded as a RTIM pulse to a refresh counter 507 where it resets thecount to zero's, forcing the end of the current refresh interval and thebeginning of the next. The output of the refresh counter 507 feeds avariable delay 506, and the variable delay 506 in turn provides therefresh count to the comparator 505. The variable delay 506 of eachcentral refresh controller slice may be configured to each provide adifferent delay, such that refresh requests, and consequently refreshgrants, are staggered. This may facilitate reduced noise due tostaggering system refresh commands to versus simultaneously issuingrefresh commands to all banks.

The central refresh controller 500 further includes refresh requestlatch 509 coupled to the comparator 505. The refresh request latch setsin response to a delayed RTIM pulse provided through comparator 505. Therefresh request latch 509 transmits a refresh request in response tobeing set, and is reset upon receipt of a refresh grant from the bankavailability model. The received refresh grant is transmitted as arefresh command to the bank controller through staging latch 511.

Hereinafter, methods of cache refresh are described in detail withreference to FIG. 6.

FIG. 6 depicts a method of cache refresh. The method 600 includesgenerating a refresh time period pulse (RTIM) at block 601. For example,the refresh time period pulse may be initiated at the beginning of arefresh time interval. A refresh time interval may be an interval duringwhich all EDRAM macros must be refreshed to retain their contents. Thus,a central refresh controller may generate a refresh time pulse every Nclock cycles, where N is the number of cycles contained in a selectedrefresh period register (e.g., normal refresh period register and/orfast refresh period register).

The method 600 further includes activating a refresh request in responseto generating the pulse at block 602. For example, the refresh requestmay be activated through a refresh request latch in a central refreshcontroller. The refresh request may be associated with a single cachememory bank.

The method 600 further includes receiving a refresh grant in response totransmitting the refresh request at block 603. The refresh grant may bereceived from a bank availability model in communication with thecentral refresh controller issuing the refresh request.

The method 600 further includes transmitting the refresh grant to a bankcontroller at block 604. The bank controller may be associated, andlocalized, at a single cache memory bank of a cache memory. The bankcontroller, upon receiving the grant, may attempt to issue refreshcommands to EDRAM macros of the single cache memory bank.

Hereinafter, a further method of cache refresh is described withreference to FIG. 7.

The method 700 includes receiving a refresh request at block 701. Forexample, the refresh request may be received at a bank availabilitymodel from a centralized refresh controller as described in FIG. 5.

The method 700 may further include suppressing bank availability atblock 702. For example, the bank availability model, in response toreceiving the refresh request from the centralized refresh controller,may suppress bank availability for functional access to the bank therefresh request is associated with.

Thereafter, the method 700 includes determining if there is a time slotavailable for a refresh grant at block 703. Upon acquiring the timeslotand granting the request at block 704, the bank availability modelreleases bank availability for functional access to continue at block705 as normal. It is noted, that if functional access is halted foranother reason through the bank availability model, full bankavailability is not released until this situation is resolved.Therefore, it should be understood that release of bank availability atblock 705 does not comprise blindly releasing availability, butreleasing bank availability for normal operations within the bankavailability model itself.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

As will be appreciated by one skilled in the art, aspects of the presentinvention may be embodied as a system, method or computer programproduct. Accordingly, aspects of the present invention may take the formof an entirely hardware embodiment, an entirely software embodiment(including firmware, resident software, micro-code, etc.) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module” or “system.”Furthermore, aspects of the present invention may take the form of acomputer program product embodied in one or more computer readablemedium(s) having computer readable program code embodied thereon.

As described above, embodiments can be embodied in the form ofcomputer-implemented processes and apparatuses for practicing thoseprocesses. In exemplary embodiments, the invention is embodied incomputer program code executed by one or more network elements.Embodiments include a computer program product 800 as depicted in FIG. 8on a computer usable medium 802 with computer program code logic 804containing instructions embodied in tangible media as an article ofmanufacture. Exemplary articles of manufacture for computer usablemedium 802 may include floppy diskettes, CD-ROMs, hard drives, universalserial bus (USB) flash drives, or any other computer-readable storagemedium, wherein, when the computer program code logic 804 is loaded intoand executed by a computer, the computer becomes an apparatus forpracticing the invention. Embodiments include computer program codelogic 804, for example, whether stored in a storage medium, loaded intoand/or executed by a computer, or transmitted over some transmissionmedium, such as over electrical wiring or cabling, through fiber optics,or via electromagnetic radiation, wherein, when the computer programcode logic 804 is loaded into and executed by a computer, the computerbecomes an apparatus for practicing the invention. When implemented on ageneral-purpose microprocessor, the computer program code logic 804segments configure the microprocessor to create specific logic circuits.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readable signalmedium or a computer readable storage medium. A computer readablestorage medium may be, for example, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, or semiconductor system,apparatus, or device, or any suitable combination of the foregoing. Morespecific examples (a non-exhaustive list) of the computer readablestorage medium would include the following: an electrical connectionhaving one or more wires, a portable computer diskette, a hard disk, arandom access memory (RAM), a read-only memory (ROM), an erasableprogrammable read-only memory (EPROM or Flash memory), an optical fiber,a portable compact disc read-only memory (CD-ROM), an optical storagedevice, a magnetic storage device, or any suitable combination of theforegoing. In the context of this document, a computer readable storagemedium may be any tangible medium that can contain, or store a programfor use by or in connection with an instruction execution system,apparatus, or device.

A computer readable signal medium may include a propagated data signalwith computer readable program code embodied therein, for example, inbaseband or as part of a carrier wave. Such a propagated signal may takeany of a variety of forms, including, but not limited to,electro-magnetic, optical, or any suitable combination thereof. Acomputer readable signal medium may be any computer readable medium thatis not a computer readable storage medium and that can communicate,propagate, or transport a program for use by or in connection with aninstruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing.

Computer program code for carrying out operations for aspects of thepresent invention may be written in any combination of one or moreprogramming languages, including an object oriented programming languagesuch as Java, Smalltalk, C++ or the like and conventional proceduralprogramming languages, such as the “C” programming language or similarprogramming languages. The program code may execute entirely on theuser's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

Aspects of the present invention are described below with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. These computer program instructions maybe provided to a processor of a general purpose computer, specialpurpose computer, or other programmable data processing apparatus toproduce a machine, such that the instructions, which execute via theprocessor of the computer or other programmable data processingapparatus, create means for implementing the functions/acts specified inthe flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computerreadable medium that can direct a computer, other programmable dataprocessing apparatus, or other devices to function in a particularmanner, such that the instructions stored in the computer readablemedium produce an article of manufacture including instructions whichimplement the function/act specified in the flowchart and/or blockdiagram block or blocks.

The computer program instructions may also be loaded onto a computer,other programmable data processing apparatus, or other devices to causea series of operational steps to be performed on the computer, otherprogrammable apparatus or other devices to produce a computerimplemented process such that the instructions which execute on thecomputer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

1. A computer program product for system refresh in a cache memory,comprising a tangible storage medium readable by a processing circuitand storing instructions for execution by the processing circuit forperforming a method comprising: generating a refresh time period (RTIM)pulse at a centralized refresh controller of the cache memory;activating a refresh request at the centralized refresh controller inresponse to generating the RTIM pulse, the refresh request associatedwith a single cache memory bank of the cache memory; receiving a refreshgrant in response to activating the refresh request; and transmittingthe refresh grant to a bank controller, the bank controller associated,and localized, at the single cache memory bank of the cache memory. 2.The computer program product of claim 1, wherein the RTIM pulse isgenerated at the beginning of a refresh time interval.
 3. The computerprogram product of claim 2, wherein the refresh time period pulsedenotes the beginning of an interval during which all embedded dynamicrandom access memory (EDRAM) macros of the single cache memory bank mustbe refreshed to retain their contents.
 4. The computer program productof claim 1, wherein the central refresh controller generates a new RTIMpulse every N clock cycles, where N is a number of clock cycles within apredetermined refresh period.
 5. The computer program product of claim4, wherein the predetermined refresh period is determined based upon atleast one of system operating voltage and system temperature of thecache memory.
 6. The computer program product of claim 1, wherein therefresh grant is received from a bank availability model incommunication with the central refresh controller activating the refreshrequest, and the bank availability model is configured to perform amethod, comprising: receiving the refresh request; suppressingavailability of the single cache memory bank in response to the receivedrefresh request; determining if there is an available time slot forgranting the refresh request; and issuing the refresh grant in responseto the determining.
 7. The computer program product of claim 1, whereina plurality of different RTIM pulses are generated for a plurality ofdifferent bank controllers, each bank controller being local to, andassociated with, only one cache memory bank of the cache memory, andeach cache memory bank of the cache memory being associated with onlyone bank controller.
 8. The computer program product of claim 7, whereinthe plurality of different RTIM pulses are staggered.
 9. A system forrefresh in a cache memory, comprising: at least one cache memory bank; abank controller local to, and in communication with, the at least onecache memory bank; a centralized refresh controller in communicationwith the bank controller, the centralized refresh controller configuredto perform a method, comprising: generating a refresh time period (RTIM)pulse at the centralized refresh controller of the cache memory;activating a refresh request at the centralized refresh controller inresponse to generating the RTIM pulse, the refresh request associatedwith the at least one cache memory bank; receiving a refresh grant inresponse to activating the refresh request; transmitting the refreshgrant to the bank controller.
 10. The system of claim 9, wherein theRTIM pulse is generating at the beginning of a refresh time interval.11. The system of claim 10, wherein the refresh time period pulsedenotes the beginning of an interval during which all EDRAM macros ofthe single cache memory bank must be refreshed to retain their contents.12. The system of claim 9, wherein the central refresh controllergenerates a new RTIM pulse every N clock cycles, where N is a number ofclock cycles of a predetermined refresh period.
 13. The system of claim12, wherein the predetermined refresh period is determined based upon atleast one of system operating voltage and system temperature of thecache memory.
 14. The system of claim 9, wherein the refresh grant isreceived from a bank availability model in communication with thecentral refresh controller activating the refresh request, and the bankavailability model is configured to perform a method, comprising:receiving the refresh request; suppressing availability of the singlecache memory bank in response to the received refresh request;determining if there is an available time slot for granting the refreshrequest; and issuing the refresh grant in response to the determining.15. The system of claim 9, wherein a plurality of different RTIM pulsesare generated for a plurality of different bank controllers, each bankcontroller being local to, and associated with, only one cache memorybank of the cache memory, and each cache memory bank of the cache memorybeing associated with only one bank controller.
 16. The system of claim15, wherein the plurality of different RTIM pulses are staggered.
 17. Acomputer implemented method of system refresh in a cache memory, themethod comprising: generating a refresh time period (RTIM) pulse at acentralized refresh controller of the cache memory; activating a refreshrequest at the centralized refresh controller in response to generatingthe RTIM pulse, the refresh request associated with a single cachememory bank of the cache memory; receiving a refresh grant in responseto activating the refresh request; and transmitting the refresh grant toa bank controller, the bank controller associated, and localized, at thesingle cache memory bank of the cache memory.
 18. The method of claim17, wherein the central refresh controller generates a new RTIM pulseevery N clock cycles, where N is a number of clock cycles of apredetermined refresh period.
 19. The method of claim 18, wherein thepredetermined refresh period is determined based upon at least one ofsystem operating voltage and system temperature of the cache memory. 20.The method of claim 17, wherein the refresh grant is received from abank availability model in communication with the central refreshcontroller activating the refresh request, and the bank availabilitymodel is configured to perform a method, comprising: receiving therefresh request; suppressing availability of the single cache memorybank in response to the received refresh request; determining if thereis an available time slot for granting the refresh request; and issuingthe refresh grant in response to the determining.
 21. The method ofclaim 17, wherein a plurality of different RTIM pulses are generated fora plurality of different bank controllers, each bank controller beinglocal to, and associated with, only one cache memory bank of the cachememory, and each cache memory bank of the cache memory being associatedwith only one bank controller.
 22. The method of claim 17, wherein theplurality of different RTIM pulses are staggered.